When the core is used to connect to an external PHY device using GMII/MII or RGMII, it is expected that the MDIO of the core is also connected to the external PHY. This allows the configuration registers of the PHY to be accessed through the Management interface of the core.
In this situation, mdio_i, mdio_o, and mdio_t must be connected to a 3-state buffer to create a bidirectional wire, mdio. This 3-state buffer can be either external to the FPGA, or internally integrated by using an IOB IOBUF component with an appropriate SelectIO™ an interface standard for the external PHY (see the following figure ).
