Receive Path Latency - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

The receive path latency is measured as the number of valid cycles between a byte being driven into the GMII/MII receive interface (gmii_rxd ), and it is appearing at the user interface (rx_axis_mac_tdata ) of the Ethernet MAC core level. So latency values do not include any GMII/MII or RGMII logic within the example design. Receiver path latency has been measured as:

  • 15 clock-enabled cycles at 1 Gbps or 2.5 Gbps Ethernet speed.
  • 15 or 15.5 clock-enabled cycles at 10 Mbps and 100 Mbps Ethernet speeds. This extra half cycle of uncertainty is due to the conversion of 4-bit MII data width to 8-bit user data conversion.