With this method, an IODelay is used on either the clock or data (or both) to adjust the clock/data relationship such that the input data is sampled at the optimum time. The ability to adjust this relationship in small increments is critical for sampling high-speed source synchronous signals. For statically aligned systems, the IODelay Tap setting is a critical part of the system, as is the requirement that the PCB is designed with precise delay and impedance-matching for all the GMII/MII or RGMII receiver data bus and control signals.
Note: You must determine the best IODelay Tap setting to ensure that
the target system has the maximum system margin to perform across voltage, temperature,
and process (multiple chips) variations.