The following table shows the optional ports added when the Physical Interface is set to Internal and Internal Mode Clock Source is set to RX User Clk2.
| Port Name and Width | Direction | Description | What to do |
|---|---|---|---|
| rx_usr_clk2 | Input | Clock for the RX datapath | Connect this port to the PCS/PMA core’s rxoutclk port |
| clk_enable_rx | Input | Clock enable for the RX datapath | Connect this port to the PCS/PMA core’s sgmii_rx_clk_en port |