I/O Standard and Placement - 9.0 English

Tri-Mode Ethernet MAC LogiCORE IP Product Guide (PG051)

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9.0 English

Among the various interfaces provided, when the TEMAC solution is generated, only the interface to the selected PHY is expected to be propagated to the actual device I/O. As such there are no specific I/O standard/placement requirements on most interfaces.

When the TEMAC is generated with either RGMII/GMII or MII support, the related interfaces and the MDIO interface, if present, are expected to propagate to device I/O and as such there are some limitations which have to be considered.

Depending upon the device family, part and package chosen there are two types of I/O available for use. HP I/O is intended for support of high speed interfaces and as such is limited to 1.8 V support. HP I/O supports both Input and Output Delays components. HR

I/O is intended for interfaces with higher voltage requirements and has a more limited supported frequency range. HR I/O only supports Input Delay components.

Both MII and GMII are 3.3 V standards, with RGMII being a 1.8 V standard. However the majority of PHYs are multi-standard and operate at either 2.5 V or 3.3 V and this is also true for the PHYs selected for AMD development boards. This means that for most applications the physical interfaces are restricted to either using HR I/O, where available, or HP I/O with an external voltage converter to translate between 1.8 V and the minimum level required by the PHY of 2.5 V. For any board design, it is important to identify which type of I/O is available/being used.

For the 1 Gbps interface standards (RGMII and GMII), the received data interface from the PHY can have some placement requirements, depending upon the capture interface used. Across all supported families there are two common capture methods used, these are detailed in 1 Gbps Ethernet MAC Core Interfaces and Tri-Speed Ethernet MAC Core Interfaces for 7 series devices and 1 Gbps Ethernet MAC Core Interfaces and Tri-Speed Ethernet MAC Core Interfaces for UltraScale architecture-based devices.

In summary, the receive data sample window is adjusted by either shifting the data using Input delays or by shifting the clock using a PLL/MMCM. When the Data is shifted a BUFIO is used to provide the lowest form of clock routing delay from the input clock to input RX signal sampling at the device IOBs. However, this creates placement constraints. A BUFIO capable clock input pin must be selected, and all other input RGMII/GMII RX signals must be placed in the respective BUFIO region. Refer the relevant family user guide. This requirement does not exist if the PLL/MMCM method is used.