In v9.0 revision 6, a new parameter, C_INT_MODE_TYPE was added. In internal mode, this indicates if the PCS/PMA core connected to TEMAC is configured for 1000BASE-X mode or SGMII mode.
In v9.0 revision 4, a new parameter, C_SGMII_CLK_SRC was added. In internal mode, this selects the clock for RX datapath.
In v9.0 of the core a new parameter, C_HAS_2G5 was added. This indicates if the core is 2.5 Gbps capable or not.
In v8.3 of the core a new parameter, C_HAS_MDIO was added. This controls the inclusion of MDIO logic.
In v8.2 of the core, a new parameter, C_PFC was added. This controls the inclusion of the PFC feature.
There are no changes in the parameters between v8.0 and v8.1 of the core.
For any version prior to v8.0, when an IP upgrade has been run in your design the Shared Logic option setting and port changes of the upgraded core are determined from the configuration of the older core as shown in the following table.
| Older Core Configuration | After IP Upgrade | |||
|---|---|---|---|---|
| Interface | Device Family | Shared Logic | Port Changes | Action |
| Internal | All | Not applicable | None | None |
| MII | All | Not applicable | None | None |
| GMII | All | Included in the core | None | None |
| RGMII | Virtex 7 | Included in the core | None | None |
| RGMII | Zynq, Artix 7 and Kintex 7 | Not part of the core | refclk removed | Remove this port and its driver from the port map on your instance(s) of this core. Also, make sure an IDELAYCTRL is instantiated in the design. Use the 'set_property IODELAY_GROUP' XDC constraint to link this IDELAYCTRL with the core (see IDELAYCTRL). |