The logic required to implement the GMII
transmitter logic is illustrated in the following figure. The gtx_clk is a user-supplied 125 MHz reference clock source for use at 1 Gbps. mii_tx_clk is sourced by the external PHY device for use at 10
Mbps and 100 Mbps speeds. Consequently, a global clock multiplexer, a BUFGMUX, is used to
switch the clock source depending on the operating speed. The output from this BUFGMUX
provides the transmitter clock for the core and user logic as illustrated in the following
figure.
Closely linked to the clock logic is the use of the
tx_enable clock enable derivation. This must be provided to the Ethernet MAC core
level. All user logic uses the AXI4-Stream interface handshaking to throttle the
data to allow for the differing data widths between the 4-bit MII and the cores 8-bit user
datapath.
The following figure also illustrates how to use the physical transmitter interface of the core to create an external GMII. The signal names and logic shown in this figure exactly match those delivered with the core for an UltraScale architecture-based device when the GMII is selected.
As shown in the following figure , the
output transmitter signals are registered in byte slice before driving them to the device
pads. The logic required to forward the transmitter clock for 1 Gbps operation is also
shown. This logic uses a byte slice output Double-Data-Rate (DDR) register so that the clock
signal produced incurs exactly the same delay as the data and control signals. This clock
signal, gmii_tx_clk , is inverted with respect to gtx_clk so that the rising edge of gmii_tx_clk occurs in the center of the data valid window, therefore maximizing setup
and hold times across the interface.
