The AXI4-Lite state machine, which is present when the core is generated with AXI4-Lite support enabled, provides basic accesses to initialize the PHY and MAC to allow basic frame transfer.
The previous figure shows the accesses performed by the state
machine. After a reset, and allowing settling time for internal resets to complete, the state
machine first writes to the MAC to enable the MDIO and configure the MDIO clock (this assumes
an s_axi_aclk running at 100 MHz). An MDIO read is then performed from PHYAD
7, which is the standard address used on AMD demonstration boards. If this
returns all 1s, it implies that no PHY exists at this location and further MDIO accesses are
skipped.
This MDIO read enables the demonstration test bench to limit the
number of MDIO accesses performed and reduce the runtime of the simulations while still
allowing the correct MDIO accesses to take place on a board. If the PHY is present, the MDIO
read data has a value other than all 1s, the state machine performs the necessary MDIO writes
to configure the PHY speed advertisement as per the mac_speed inputs. If
RGMII is selected, a read-modify-write is performed to select RGMII, unless the PHY is only
RGMII, avoiding the need to change jumper settings on the board. Finally the PHY is reset and
auto-negotiation restarted.
After auto-negotiation completes the MAC speed
is updated, as per the mac_speed inputs. The MAC is then
configured to disable flow control. If Frame Filter is enabled, initialize Frame Filter value
and mask value bytes [11:0] and set the address filter to promiscuous mode if the PHY is
present or if the MAC data rate is set to 2.5 Gbps, or to non-promiscuous mode if the PHY is
not present.
If Frame Filter is disabled, initialize the
unicast address and set the Frame Filter to promiscuous mode. If the AVB Endpoint logic is
present, then the RTC is started and PTP frames both transmitted and received (this assumes an
external loopback is in use). Finally the state machine sits and waits, if the update_speed input asserts it returns to the initial MDIO read
state and the new mac_speed input is captured and applied.
With the state machine only applying a fixed
core configuration, logic can be stripped during logic optimization. To avoid this, the state
machine has a serial interface, serial_command and serial_response , which can be used to access any location and
either perform a read or a write. This uncertainty prevents functions unused by the state
machine from being stripped.