The RX PTP packet buffer is illustrated in the following figure. This provides working memory to hold each received PTP frame. The software drivers, using the AXI4-Lite configuration bus, can then read and decode the contents of the received PTP frames. The PTP packet buffer is implemented in dual-port block RAM. Port A of the block RAM is connected to the configuration bus and all addresses in the buffer can be read (writes are not allowed). Port B of the block RAM is connected to the PTP frame filter, which routes all received PTP frames into the RX PTP Packet Buffer. The RX PTP Packet Buffer is divided into 16 identical buffer sections as illustrated. Each section contains 256 bytes, which are formatted as follows:
- The PTP frame data itself is stored from address 0 onwards: the entire MAC frame from the Destination Address onwards is written (with the exception of the FCS field which has been removed by the receive logic). The number of addresses used is dependent on the particular PTP frame size, which is different for each PTP frame type. Each PTP buffer provides a maximum of 252 bytes (more than that required for the largest PTP frame). When an oversized PTP frame is received, the first 252 bytes is captured and stored, and other bytes are lost.
- The top four addresses of each buffer, from address 0xFC to 0xFF are reserved for a timestamp field. At the beginning of PTP frame reception, the Timestamping Logic samples the Real-Time Clock. Following the end of PTP frame reception, this captured timestamp is automatically written into this location to accompany the frame for which it was taken.
Following reset, the first received PTP frame is written into Buffer Number 0. The next subsequent received PTP frame is written into the next available buffer—in this case, number 1. This process continues with buffer numbers 2, 3, then 4,... being used. After receiving the 1sixth PTP frame (which would have been stored in buffer number 15), the count is reset, and then buffer number 0 is overwritten with the next received PTP frame. For this reason, at any one time the RX PTP Packet Buffer is capable of storing the most recently received 16 PTP frames.
Following the completion of PTP frame reception, a
dedicated interrupt signal, interrupt_ptp_rx , is generated by the core. On the
assertion of the interrupt, the captured timestamp is already available in the upper four
bytes of the buffer, and the rx_packet field of the RX PTP Packet Buffer Control Register
indicates the most recently filled Buffer Number. The software drivers available from AMD using the AXI4-Lite and dedicated interrupt, use this interface
to decode, and then act on the received PTP packet information.
