Verilog Coding Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

All addressable words are initialized to the same value.

reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];

integer i;

initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

end