VHDL Component Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

entity rtl of test is

attribute dont_touch : string;

   component my_comp

   port (

   in1 : in std_logic;

   out1 : out std_logic);

end component;

attribute dont_touch of my_comp : component is "yes";