UltraRAM Coding Templates - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

UltraRAM is described in "Chapter 2, UltraRAM Resources" of the UltraScale Architecture Memory Resources User Guide (UG573) [Ref 3] as follows:

"UltraRAM is a single-clocked, two port, synchronous memory available in UltraScale+™ devices. Because UltraRAM is compatible with the columnar architecture, multiple UltraRAMs can be instantiated and directly cascaded in an UltraRAM column for the entire height of the device. A column in a single clock region contains 16 UltraRAM blocks. Devices with UltraRAM include multiple UltraRAM columns distributed in the device. Most of the devices in the UltraScale+ family include UltraRAM blocks. For the available quantity of UltraRAM in specific device families, see the UltraScale Architecture and Product Overview (DS890) [Ref 1].

The following files are included in the Coding Examples:

xilinx_ultraram_single_port_no_change.v 

xilinx_ultraram_single_port_no_change.vhd 

xilinx_ultraram_single_port_read_first.v 

xilinx_ultraram_single_port_read_first.vhd 

xilinx_ultraram_single_port_write_first.v

xilinx_ultraram_single_port_write_first.vhd 

The Vivado tool includes templates of UltraRAM VHDL and Verilog code. The following figure shows the template files.

Figure 4-2:      UltraRAM Coding Templates

X-Ref Target - Figure 4-2

20171-Ultra_RAM-Language_Templates.png

See the UltraScale Architecture Memory Resources User Guide (UG573) [Ref 3] for more information.