RAM_DECOMP Example (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID: UG901
Release Date: 2022-06-06
Version: 2022.1 English

(* ram_decomp = "power" *) reg [data_size-1:0] myram [2**addr_size-1:0];