USE_DSP - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

Note:   This attribute is renamed from USE_DSP48 to recognize that some of the newer DSP blocks are different sizes. Using the attribute USE_DSP48 still works even with the DSPs of different sizes.


RECOMMENDED:   Xilinx recommends that you change any USE_DSP48 to the new attribute name, USE_DSP.

USE_DSP instructs the synthesis tool how to deal with synthesis arithmetic structures.
By default, unless there are timing concerns or threshold limits, synthesis attempts to infer mults, mult-add, mult-sub, and mult-accumulate type structures into DSP blocks.

Adders, subtracters, and accumulators can go into these blocks also, but by default are implemented with the logic instead of with DSP blocks. The USE_DSP attribute overrides the default behavior and force these structures into DSP blocks.

Accepted values are: "logic", "simd", "yes", and "no":

The "logic" value is used specifically for XOR structures to go into the DSP primitives. For "logic", this attribute can be placed on the module/architecture level only.   

The "simd" is used to instruct the tool to put SIMD structures (Single-instruction-multiple-data) into DSPs. Please see the templates for examples.

The "yes" and "no" values instruct the tool to either put the logic into a DSP or not. These values can be placed in the RTL on signals, architecture, components, entities, and modules. The priority is: 1. Signals. 2. Architectures and components. 3. Modules and entities.

If the attribute is not specified, the default behavior is for Vivado synthesis to determine the correct behavior. This attribute can be set in the RTL or the XDC.