Tcl Script Example - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

The following is an example synth_design Tcl script:

# Setup design sources and constraints

read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]

read_vhdl ./Sources/hdl/bft.vhdl

read_verilog [ glob ./Sources/hdl/*.v ]

read_xdc ./Sources/bft_full.xdc

# Run synthesis

synth_design -top bft -part xc7k70tfbg484-2 -flatten_hierarchy rebuilt

# Write design checkpoint

write_checkpoint -force $outputDir/post_synth

# Write report utilization and timing estimates

report_utilization -file utilization.txt

report_timing > timing.txt