Instantiating the Lower-Level Netlist in a Design - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

To run the top-level design with the lower-level netlist or third-party netlist, instantiate the lower-level as a black box by providing a description of the port in a lower-level to the Vivado tool. In the Setting a Bottom-Up Out-of-Context Flow, this is referred to as a stub file.


IMPORTANT:   The port names provided to the Vivado tool and the port names in the netlist must match.

In VHDL, describe the ports with a component statement, as shown in the following code snippet:

component <name>

      port (in1, in2 : in std_logic;

         out1 : out std_logic);

end component;

Because Verilog does not have an equivalent of a component, use a wrapper file to communicate the ports to the Vivado tool. The wrapper file looks like a typical Verilog file, but contains only the ports list, as shown in the following code snippet:

module <name> (in1, in2, out1);

   input in1, in2;

   output out1;