Blocking Procedural Assignment Syntax Example Two (Alternate) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

if (in1) out = 1’b0;

else out = in2;

This assignment blocks the current process from continuing to execute additional statements at the same time, and is used mainly in simulation.

For more information regarding Verilog format for Vivado simulation, see this link to the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 11].