NOT RECOMMENDED Coding Example WITH Buffer Port Mode - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

entity alu is

   port(

      CLK : in STD_LOGIC;

      A : inSTD_LOGIC_VECTOR(3 downto 0);

      B : inSTD_LOGIC_VECTOR(3 downto 0);

      C : buffer STD_LOGIC_VECTOR(3 downto 0));

end alu;

 

architecture behavioral of alu is

begin

   process begin

      if rising_edge(CLK) then

         C <= UNSIGNED(A) + UNSIGNED(B) UNSIGNED(C);

      end if;

   end process;

end behavioral;