Example of for-generate Statement (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

In this coding example, the for-generate statement describes the calculation of the result and carry out for each bit position of this 8-bit Adder.

Filename: for-generate.vhd



-- A for-generate example


-- for_generate.vhd


entity for_generate is


 A, B : in  BIT_VECTOR(0 to 7);

 CIN  : in  BIT;

 SUM  : out BIT_VECTOR(0 to 7);

 COUT : out BIT


end for_generate;


architecture archi of for_generate is

signal C : BIT_VECTOR(0 to 8);


C(0) <= CIN;

COUT <= C(8);

LOOP_ADD : for I in 0 to 7 generate

 SUM(I)   <= A(I) xor B(I) xor C(I);

 C(I + 1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));

end generate;

end archi;