8-Bit Shift Register Coding Example One (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

This coding example uses a concatenation to describe the Register chain.

Filename: shift_registers_0.v

 

//  8-bit Shift Register

//  Rising edge clock

//  Active high clock enable

//  Concatenation-based template

//  File: shift_registers_0.v

 

module shift_registers_0 (clk, clken, SI, SO);

parameter WIDTH = 32;

input clk, clken, SI;

output SO;

 

reg [WIDTH-1:0] shreg;

 

always @(posedge clk)

 begin

   if (clken)

     shreg = {shreg[WIDTH-2:0], SI};

 end

 

assign SO = shreg[WIDTH-1];

 

endmodule