VHDL Architecture Declaration Coding Example - 2022.1 English

ibrary IEEE;

use IEEE.std_logic_1164.all;

 

entity EXAMPLE is

port (

   A,B,C : in std_logic;

   D,E : out std_logic );

end EXAMPLE;

 

architecture ARCHI of EXAMPLE is

   signal T : std_logic;

begin

...

end ARCHI;