Pipelining the RAM - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

The UltraRAM (URAM) supports pipelining registers into the RAM. This becomes especially useful when multiple UltraRAMs are used to create a very large RAM. To fully pipeline the RAM, you must add extra registers to the output of the RAM in RTL. To calculate the number of pipeline registers to use, add together the number of rows and columns in the RAM matrix.

Note:   The tool does not create the pipeline registers for you; they must be in the RTL code for Vivado synthesis to make use of them.

The synthesis log file has a section about URAMs and how many rows and columns are used to create the RAM matrix. You can use this section to add pipeline registers in the RTL.

To calculate the number of rows and columns of the matrix yourself, remember that the UltraRAM is configured as a 4Kx72.

To calculate the number of rows take your address space of the RAM in RTL and divide by 4K. If this number is higher than the number specified by CASCADE_HEIGHT, then remove the extra RAMs, and start them on a new column in the log.