Initializing Block RAM From an External Data File (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Filename: rams_init_file.v

 

 

 

// Initializing Block RAM from external data file

// Binary data

// File: rams_init_file.v

 

module rams_init_file (clk, we, addr, din, dout);

input clk;

input we;

input [5:0] addr;

input [31:0] din;

output [31:0] dout;

 

reg [31:0] ram [0:63];

reg [31:0] dout;

 

initial begin

$readmemb("rams_init_file.data",ram);

end

 

always @(posedge clk)

begin

 if (we)

    ram[addr] <= din;

 dout <= ram[addr];

end endmodule

 

 

Note:   The external file that is used to initialize the RAM needs to be in bit vector form. External files in integer or hex format will not work.