VHDL-2008 allows you to form an array aggregate and then assign it to multiple places all in one statement.
For example if in1 where defined as a std_logic_vector(3 downto 0):
(my_reg1, my_reg2, enable, reset) <= in1;
This example assigns all four signals to the individual bits of in1:
my_reg1 gets in1(3)
my_reg2 gets in1(2)
enable is in1(1)
reset is in1(0)
In addition, these signals can be assigned out of order, as shown in the following example:
(1=> enable, 0 => reset, 3 => my_reg1, 2 => my_reg2) <= in1;