VHDL Coding Examples - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

type ram_type is array (0 to 31) of std_logic_vector(19 downto 0);

signal RAM : ram_type :=

(

   X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A", X"00300", X"08602",    X"02310", X"0203B", X"08300", X"04002", X"08201", X"00500", X"04001", X"02500",    X"00340", X"00241", X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",    X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021", X"0030D", X"08201"

);

All bit positions are initialized to the same value:

type ram_type is array (0 to 127) of std_logic_vector (15 downto 0);

signal RAM : ram_type := (others => (others => '0'));