Generate Statements - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

Behavioral Verilog generate statements:

Allow you to create:

°parameterized and scalable code.

°Repetitive or scalable structures.

°Functionality conditional on a particular criterion being met.

Are resolved during Verilog elaboration.

Are conditionally instantiated into your design.

Are described within a module scope.

Start with a generate keyword.

End with an endgenerate keyword.