VHDL Predefined Enumerated Types - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Vivado synthesis supports the following predefined VHDL enumerated types.

Table 5-1:      VHDL Enumerated Type Summary

Enumerated Type

Defined In

Allowed Values

bit

standard package

0 (logic zero)

1 (logic 1)

boolean

standard package

false

true

std_logic

IEEE std_logic_1164 package

See std_logic Allowed Values.