A VHDL variable is:
•Declared in a process or a subprogram.
•Used within that process or subprogram.
•Assigned with the := assignment operator.
variable var1 : std_logic_vector (7 downto 0); var1 := "01010011";
A VHDL variable is:
•Declared in a process or a subprogram.
•Used within that process or subprogram.
•Assigned with the := assignment operator.
variable var1 : std_logic_vector (7 downto 0); var1 := "01010011";