Syntax Example (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

signal debug_wire : std_logic;

attribute MARK_DEBUG : string;

-- Marks an internal wire for debug

attribute MARK_DEBUG of debug_wire : signal is "TRUE";