Simple Dual-Port Block RAM with Single Clock (Verilog) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Filename: simple_dual_one_clock.v

// Simple Dual-Port Block RAM with One Clock

// File: simple_dual_one_clock.v

 

module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);

 

input clk,ena,enb,wea;

input [9:0] addra,addrb;

input [15:0] dia;

output [15:0] dob;

reg [15:0] ram [1023:0];

reg [15:0] doa,dob;

 

always @(posedge clk) begin

if (ena) begin

   if (wea)

       ram[addra] <= dia;

end

end

 

always @(posedge clk) begin

 if (enb)

   dob <= ram[addrb];

end

 

endmodule