VHDL Entity Example - 2022.1 English

entity example_dt_vhd is

port (

   clk : in std_logic;

   In1 : in std_logic;

   In2 : in std_logic;

   out1 : out std_logic

);

   attribute dont_touch : string;

   attribute dont_touch of example_dt_vhd : entity is "true|yes";

end example_dt_vhd;