Example of case Statement (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

library IEEE;

use IEEE.std_logic_1164.all;

 

entity mux4 is port (

   a, b, c, d : in std_logic_vector (7 downto 0);

   sel : in std_logic_vector (1 downto 0);

   outmux : out std_logic_vector (7 downto 0));

end mux4;

 

architecture behavior of mux4 is begin

process (a, b, c, d, sel)

begin

      case sel is

      when "00" => outmux <= a;

      when "01" => outmux <= b;

      when "10" => outmux <= c;

      when others => outmux <= d; -- case statement must be complete

   end case;

   end process;

end behavior;