VHDL Sequential Logic - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

A VHDL process is sequential (as opposed to combinatorial) when some assigned signals are not explicitly assigned in all paths within the process. The generated hardware has an internal state or memory (Flip-Flops or Latches).


RECOMMENDED:   Use a sensitivity-list based description style to describe sequential logic.

Describing sequential logic using a process with a sensitivity list includes:

The clock signal

Any optional signal controlling the sequential element asynchronously (asynchronous set/reset)

An if statement that models the clock event.