Unacceptable Example Two - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Do not mix blocking and non-blocking assignments for different bits of the same signal.

if (in2)

begin

   out1[0] = 1'b0;

   out1[1] <= in1;

end else begin

   out1[0] = in2;

   out1[1] <= 1'b1;

end