MAX_FANOUT - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

MAX_FANOUT instructs Vivado synthesis on the fanout limits for registers and signals. You can specify this either in RTL or as an input to the project. The value is an integer.

This attribute only works on registers and combinatorial signals. To achieve the fanout, it replicates the register or the driver that drives the combinatorial signal. This attribute can be set only in the RTL.

Note:   Inputs, black boxes, EDIF (EDF), and Native Generic Circuit (NGC) files are not supported.


IMPORTANT:   NGC format files are not supported in the Vivado Design Suite for UltraScale devices. It is recommended that you regenerate the IP using the Vivado Design Suite IP customization tools with native output products. Alternatively, you can use the NGC2EDIF command to migrate the NGC file to EDIF format for importing. However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format files going forward.


RECOMMENDED:   Using MAX_FANOUT attributes on global high fanout signals leads to sub-optimal replication in synthesis. For this reason, Xilinx recommends only using MAX_FANOUT inside the hierarchies on local signals with medium to low fanout.