Verilog allows you to separate HDL source code into more than one file. To reference the code in another file, use the following syntax in the current file.
`include <path/file-to-be-included>
The above line will take the contents of the file to be included and insert it all into the current file at the line with the `include.
The path can be a relative or an absolute path. In the case of a relative path, the Verilog compiler will look in two different places for the file to be included.
°The first is relative to the file with the `include statement. The compiler will look there, and if it can find the file, it will insert the contents of the file there.
°The second place it will look is relative to the -include_dirs option that is in the Verilog options section of the General settings.
Multiple `include statements are allowed in the same Verilog file.