Vivado synthesis infers cascades of multiply-add to compose FIR filters directly from RTL.
There are several possible implementations of such filters; one example is the systolic filter described in the 7 Series DSP48E1 Slice User Guide (UG479) [Ref 2] and shown in the "8-Tap Even Symmetric Systolic FIR" (Figure 3-6).
Download the coding example files from Coding Examples.