Sequential always Block Examples - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

This coding example describes an 8-bit register with a rising-edge clock. There are no other control signals.

module seq1 (DI, CLK, DO);

   input [7:0] DI;

   input CLK;

   output [7:0] DO;

   reg [7:0] DO;

 

   always @(posedge CLK) DO <= DI ;

      endmodule

The following code example adds an active-High asynchronous reset.

module EXAMPLE (DI, CLK, ARST, DO);

   input [7:0] DI;

   input CLK, ARST;

   output [7:0] DO;

   reg [7:0] DO;

 

always @(posedge CLK or posedge ARST)

if (ARST == 1'b1)

   DO <= 8'b00000000;

else

   DO <= DI;

endmodule

 

The following code example describes an active-High asynchronous reset and an active-Low asynchronous set:

module EXAMPLE (DI, CLK, ARST, ASET, DO);

   input [7:0] DI;

   input CLK, ARST, ASET;

   output [7:0] DO;

   reg [7:0] DO;

 

always @(posedge CLK or posedge ARST or negedge ASET)

if (ARST == 1'b1)

   DO <= 8'b00000000;

elsif (ASET == 1'b1) DO <= 8'b11111111;

else

 

      DO <= DI;

endmodule

The following code example describes a register with no asynchronous set/reset, and a synchronous reset.

module EXAMPLE (DI, CLK, SRST, DO);

   input [7:0] DI;

   input CLK, SRST;

   output [7:0] DO;

   reg [7:0] DO;

 

always @(posedge CLK)

   if (SRST == 1'b1)

      DO <= 8'b00000000;

   else

      DO <= DI;

endmodule