KEEP Example (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

signal sig1 : std_logic;

attribute keep : string;

attribute keep of sig1 : signal is "true";

....

....

sig1 <= in1 and in2;

out1 <= sig1 and in3;