The Tcl command to run synthesis is synth_design. Typically, this command is run with multiple options, for example:
synth_design -part xc7k30tfbg484-2 -top my_top
In this example, synth_design is run with the -part option and the -top option.
In the Tcl Console, you can set synthesis options and run synthesis using Tcl command options. To retrieve a list of options, type synth_design -help in the Tcl Console. The following snippet is an example of the -help output: synth_design -help.
Description:
Synthesize a design using Vivado Synthesis and open that design
Syntax:
synth_design [-name <arg>] [-part <arg>] [-constrset <arg>] [-top <arg>]
[-include_dirs <args>] [-generic <args>] [-verilog_define <args>]
[-flatten_hierarchy <arg>] [-gated_clock_conversion <arg>]
[-directive <arg>] [-rtl] [-bufg <arg>] [-no_lc]
[-shreg_min_size <arg>] [-mode <arg>]
[-fsm_extraction <arg>][-rtl_skip_mlo][-rtl_skip_ip]
[-rtl_skip_constraints]
[-keep_equivalent_registers] [-resource_sharing <arg>]
[-cascade_dsp <arg>] [-control_set_opt_threshold <arg>]
[-max_bram <arg>] [-max_uram <arg>]
[-max_dsp <arg>] [-max_bram_cascade_height <arg>]
[-max_uram_cascade_height <arg>] [-retiming] [-no_retimimg]
[-no_srlextract]
[-assert] [-no_timing_driven] [-sfcu] [-debug_log] [-quiet] [-verbose]
Returns:
design object
Usage:
Name Description
-----------------------------------------
[-name] Design name
[-part] Target part
[-constrset] Constraint fileset to use
[-top] Specify the top module name
[-include_dirs] Specify verilog search directories
[-generic] Specify generic parameters. Syntax: -generic
<name>=<value> -generic <name>=<value> ...
[-verilog_define] Specify verilog defines. Syntax:
-verilog_define <macro_name>[=<macro_text>]
-verilog_define <macro_name>[=<macro_text>]
[-flatten_hierarchy] Flatten hierarchy during LUT mapping. Values:
full, none, rebuilt
Default: rebuilt
[-gated_clock_conversion] Convert clock gating logic to flop enable.
Values: off, on, auto
Default: off
[-directive] Synthesis directive. Values: default,
RuntimeOptimized, AreaOptimized_high,
AreaOptimized_medium, AlternateRoutability,
AreaMapLargeShiftRegToBRAM,
AreaMultThresholdDSP, FewerCarryChains
Default: default
[-rtl] Elaborate and open an rtl design
[-bufg] Max number of global clock buffers used by
synthesis
Default: 12
[-no_lc] Disable LUT combining. Do not allow combining
[-shreg_min_size] Minimum length for chain of registers to be
mapped onto SRL
Default: 3
[-mode] The design mode. Values: default,
out_of_context
Default: default
[-fsm_extraction] FSM Extraction Encoding. Values: off,
one_hot, sequential, johnson, gray,
user_encoding, auto
Default: auto
[-rtl_skip_mlo] Skip mandatory logic optimization for RTL
elaboration of the design; requires -rtl option.
[-rtl_skip_ip] Exclude subdesign checkpoints in the RTL
elaboration of the design; requires -rtl
option.
[-rtl_skip_constraints] Do not load and validate constraints against
elaborated design; requires -rtl option.
[-srl_style] Static SRL Implementation Style. Values: register,
srl, srl_reg, reg_srl, reg_srl_reg
[-keep_equivalent_registers] Prevents registers sourced by the same logic
from being merged. (Note that the merging can
otherwise be prevented using the synthesis
KEEP attribute)
[-resource_sharing] Sharing arithmetic operators. Value: auto,
on, off
Default: auto
[-cascade_dsp] Controls how adders summing DSP block outputs
will be implemented. Value: auto, tree, force
Default: auto
[-control_set_opt_threshold] Threshold for synchronous control set
optimization to lower number of control sets.
Valid values are 'auto' and non-negative
integers. The higher the number, the more
control set optimization will be performed
and fewer control sets will result. To
disable control set optimization completely,
set to 0.
Default: auto
[-max_bram] Maximum number of block RAM allowed in
design. (Note -1 means that the tool will
choose the max number allowed for the part in
question)
Default: -1
[-max_uram] Maximum number of UltraRAM blocks allowed in
design. (Note -1 means that the tool will
choose the max number allowed for the part in
question)
Default: -1
[-max_dsp] Maximum number of block DSP allowed in
design. (Note -1 means that the tool will
choose the max number allowed for the part in
question)
Default: -1
[-max_bram_cascade_height] Controls the maximum number of BRAM that can
be cascaded by the tool. (Note -1 means that
the tool will choose the max number allowed
for the part in question)
Default: -1
[-max_uram_cascade_height] Controls the maximum number of UtraRAM that can
be cascaded by the tool. (Note -1 means that
the tool will choose the max number allowed
for the part in question)
Default: -1
[-retiming] Seeks to improve circuit performance for
intra-clock sequential paths by automatically
moving registers (register balancing) across
combinatorial gates or LUTs. It maintains
the original behavior and latency of the
circuit and does not require changes to the
RTL sources. This is for non Versal devices only.
[-no_retimiming ] For Versal devices only. Turns off the retiming
features that are on by default in Versal.
[-no_srlextract] Prevents the extraction of shift registers so
that they get implemented as simple registers
[-assert] Enable VHDL assert statements to be
evaluated. A severity level of failure will
stop the synthesis flow and produce an error.
[-no_timing_driven] Do not run in timing driven mode.
[-sfcu] Run in single-file compilation unit mode.
[-debug_log] Print detailed log files for debugging
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command
execution
For the -generic option, special handling needs to happen with VHDL boolean and std_logic_vector type because those type do not exist in other formats. Instead of TRUE, FALSE, or 0010, for example, Verilog standards should be given.
For boolean, the value for FALSE is:
-generic my_gen=1‘b0
For std_logic_vector, the value for 0010 is:
-generic my_gen=4‘b0010
IMPORTANT: Overriding string generics or parameters is not supported.
IMPORTANT: If you are using the -mode out_of_context option on the top-level, do not use the PACKAGE_PIN property unless there is an I/O buffer instantiated in the RTL. The out_of_context option tells the tool to not infer any I/O buffers including tristate buffers. Without the buffer, you will get errors in placer.
A verbose version of the help is available in the Vivado Design Suite Tcl Command Reference Guide (UG835) [Ref 4]. To determine any Tcl equivalent to a Vivado IDE action, run the command in the Vivado IDE and review the content in the Tcl Console or the log file.