Variables in Behavioral Verilog - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

Variables in behavioral Verilog are declared as an integer.

These declarations are used in test code only. Verilog provides data types such as reg and wire for actual hardware description.

The difference between reg and wire depends on whether the variable is given its value in a procedural block (reg) or in a continuous assignment (wire).

°Both reg and wire have a default width of one bit (scalar).

°To specify an N-bit width (vectors) for a declared reg or wire, the left and right bit positions are defined in square brackets separated by a colon.

°In Verilog-2001, reg and wire data types can be signed or unsigned.