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VHDL Construct
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Support Status
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VHDL Entity Headers
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Generics
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Supported
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Ports
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Supported, including unconstrained ports
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Entity Statement Part
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Unsupported
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VHDL Packages
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Supported
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VHDL Physical Types
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TIME
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Supported, but only in functions for constant calculations.
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REAL
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Supported, but only in functions for constant calculations.
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VHDL Modes
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Linkage
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Unsupported
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VHDL Declarations
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Type
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Supported for the following:
•Enumerated types
•Types with positive range having constant bounds
•Bit vector types
•Multi-dimensional arrays
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VHDL Objects
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Constant Declaration
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Supported except for deferred constant
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Signal Declaration
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Supported except for register and bus type signals.
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Attribute Declaration
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Supported for some attributes, otherwise skipped.
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VHDL Specifications
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HIGHLOW
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Supported
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LEFT
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Supported
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RIGHT
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Supported
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RANGE
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Supported
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REVERSE_RANGE
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Supported
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LENGTH
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Supported
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POS
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Supported
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ASCENDING
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Supported
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Configuration
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Supported only with the all clause for instances list.
•If no clause is added, Vivado synthesis looks for the entity or architecture compiled in the default library.
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Disconnection
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Unsupported
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Underscores
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Object names can contain underscores in general (DATA_1), but Vivado synthesis does not allow signal names with leading underscores ( _DATA_1).
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VHDL Operators
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Logical Operators: and, or, nand, nor, xor, xnor, not
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Supported
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Relational Operators: =, /=, <, <=, >, >=
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Supported
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& (concatenation)
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Supported
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Adding Operators: +, -
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Supported
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*
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Supported
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/
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Supported if the right operand is a constant power of 2, or if both operands are constant.
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Rem
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Supported if the right operand is a constant power of 2.
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Mod
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Supported if the right operand is a constant power of 2.
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Shift Operators: sll, srl, sla, sra, rol, ror
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Supported
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Abs
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Supported
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**
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Supported if the left operand is 2.
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Sign: +, -
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Supported
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VHDL Operands
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Abstract Literals
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Only integer literals are supported.
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Physical Literals
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Ignored
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Enumeration Literals
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Supported
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String Literals
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Supported
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Bit String Literals
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Supported
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Record Aggregates
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Supported
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Array Aggregates
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Supported
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Function Call
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Supported
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Qualified Expressions
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Supported for accepted predefined attributes.
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Types Conversions
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Supported
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Allocators
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Unsupported
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Static Expressions
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Supported
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Wait Statement
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Wait on sensitivity_list until boolean_expression.
See VHDL Combinatorial Circuits.
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Supported with one signal in the sensitivity list and in the boolean expression.
•Multiple wait statements are not supported.
•wait statements for Latch descriptions are not supported.
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Wait for time_expression.
See VHDL Combinatorial Circuits.
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Unsupported
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Assertion Statement
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Supported for static conditions only.
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Signal Assignment Statement
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Supported.
Delay is ignored.
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Variable Assignment Statement
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Supported
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Procedure Call Statement
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Supported
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If Statement
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Supported
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Case Statement
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Supported
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Loop Statements
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Next Statements
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Supported
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Exit Statements
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Supported
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Return Statements
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Supported
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Null Statements
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Supported
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Concurrent Statements
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Process Statement
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Supported
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Concurrent Procedure Call
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Supported
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Concurrent Assertion Statements
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Ignored
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Concurrent Signal Assignments
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Supported, except after clause, transport or guarded options, or waveforms.
UNAFFECTED is supported.
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Component Instantiation Statements
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Supported
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for-generate
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Statement supported for constant bounds only
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if-generate
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Statement supported for static condition only
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