Legal Statements - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
Release Date
2022.1 English

Vivado synthesis supports behavioral Verilog legal statements.

The following statements (variable and signal assignments) are legal:

°variable = expression

°if (condition) statement

°else statement

°case (expression), for example:

   expression: statement


   default: statement


°for (variable = expression; condition; variable = variable + expression) statement

°while (condition) statement

°forever statement

°functions and tasks

All variables are declared as integer or reg.

A variable cannot be declared as a wire.