Describing a Clock Enable in the wait Statement Example (VHDL) - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

You can describe a clock enable (clken) in the wait statement together with the clock.

process begin

   wait until rising_edge(clk) and clken = '1';

   q <= d;

end process;