Vivado synthesis supports the some predefined VHDL IEEE packages, which are pre-compiled in the IEEE library, and the following IEEE packages:
•numeric_bit
°Unsigned and signed vector types based on bit.
°Overloaded arithmetic operators, conversion functions, and extended functions for these types.
•std_logic_1164
°std_logic, std_ulogic, std_logic_vector, and std_ulogic_vector types.
°Conversion functions based on these types.
•numeric_std
°Unsigned and signed vector types based on std_logic.
°Overloaded arithmetic operators, conversion functions, and extended functions for these types. Equivalent to std_logic_arith.
•fixed_pkg
°For fixed variable and pin types.
°use ieee.fixed_pkg.all;
•float_pkg
°For floating variable and pin types.
°use ieee.float_pkg.all;