Buffer Port Mode - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English


RECOMMENDED:   Do not use buffer port mode.

VHDL allows buffer port mode when a signal is used both internally, and as an output port when there is only one internal driver. Buffer ports are a potential source of errors during synthesis, and complicate validation of post-synthesis results through simulation.