Supported VHDL Types - 2022.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English
Table 5-4:      Supported VHDL Bit Vector Types

Type

Defined In Package

Models

bit_vector

Standard

Vector of bit elements

std_logic_vector

IEEE std_logic_1164

Vector of std_logic elements
Table 5-5:      Supported VHDL Overloaded Types

Type

Defined In IEEE Package

std_ulogic_vector

std_logic_1164

unsigned

numeric_std

signed

numeric_std

unsigned

std_logic_arith (Synopsys)

signed

std_logic_arith (Synopsys)