FSM Registers - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

Specify a reset or power-up state for Vivado synthesis to identify a Finite State Machine (FSM) or set the value of FSM_ENCODING to "none".

The State Register can be asynchronously or synchronously reset to a particular state.


RECOMMENDED:   Use synchronous reset logic over asynchronous reset logic for an FSM.