Targeting SystemVerilog for a Specific File - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2022.1 English

By default, the Vivado synthesis tool compiles *.v files with the Verilog 2005 syntax and *.sv files with the SystemVerilog syntax.

To target SystemVerilog for a specific *.v file in the Vivado IDE, right-click the file, and select Source Node Properties. In the Source File Properties window, change the File Type to SystemVerilog, and click OK.