DIRECT_RESET VHDL Example - 2022.1 English

entity test is port(

   in1 : std_logic_vector (8 downto 0);

   clk : std_logic;

   rst1, rst2, rst3 : in std_logic

   out1 : std_logic_vector(8 downto 0));

   attribute direct_reset : string;

   attribute direct_reset of rst3: signal is "yes";

 

end test;